This application claims the priority benefit of Taiwan application serial no. 89124067, filed Nov. 14, 2000.
1. Field of the Invention
The present invention relates to metal oxide semiconductor (MOS). More particularly, the present invention relates to self-aligned contact method of fabrication.
2. Description of the Related Art
Etching technology for Self-aligned contact etching has become an essential technology for one quarter micron devices or those with even smaller device size. Self-aligned contact etching can be used on devices that are highly integrated and have high operating speed. It is necessary to continuously improve the technology.
In the conventional method of fabricating a self-aligned contact (SAC), a silicon nitride cap layer and silicon nitride spacer are usually formed on a gate. A dielectric layer is then formed over the substrate. Photolithography and etching technologies are performed to form a self-aligned silicide contact opening in. the, dielectric layer. The self-aligned contact opening is then filled with conductive material to complete the fabrication of a self-aligned contact (SAC).
In the conventional method described above, the silicon nitride cap layer and the silicon nitride spacer are formed in order to utilize the differences of etching selectivity between the silicon dioxide dielectric layer and the silicon nitride cap layer and spacer, which enables a self-aligned contact opening to be formed in a later step.
Anisotropic dry etching is usually used in the conventional method of forming a (SAC) opening to remove the dielectric layer above the source/drain region. Anisotropic over-etching is performed to insure that the dielectric layer can be removed completely. Because there is not much difference of the etching selectivity for the silicon oxide dielectric layer to silicon nitride layer and the silicon nitride spacer, the silicon nitride of the cap layer and gate spacer may be etched too much. Over-etching may even also cause damage on the spacer comer. As a result, when the self-aligned contact opening is filled with conductive layer, the damage of the spacer may cause a parasitic capacitor between the gate and the conductive layer due to the separation is too small. Even worse, a short circuit between the gate and the conductive layer may occur, causing failure of the device.
Moreover, in the conventional method for solving the above problem by increasing the thickness of the silicon nitride spacer may cause a reduction of integration.
The present invention uses an undoped polysilicon gate spacer and takes properties of hight etching selectivity between polysilicon and silicon nitride for forming a contact opening. The high etching selectivity of the polysilicon and silicon nitride allows the gate with greater protection, which can prevent parasitic capacitance or short-circuiting.
As embodied and broadly described herein, the invention provides a method of fabricating a self-aligned contact of a semiconductor device. A substrate with an isolation structure is provided. A gate oxide layer, a conductive gate on the gate oxide layer, a cap layer on the conductive gate, and a source/drain are formed consecutively on the substrate. A conformal buffer layer is formed over the substrate. An undoped polysilicon gate spacer is then formed on sidewall of the gate. A dielectric layer is then formed over the substrate. Photolithography and etching technologies are used to form a self-aligned contact opening in the dielectric layer and the conformal buffer layer. The self-aligned contact opening is filled with a conductive layer to form a self-aligned contact.
The self-aligned contact is formed the method of the present invention using undoped polysilicon as the material for the gate spacer. Due to the high etching selectivity between polysilicon and silicon oxide, the protection to the gate can be enhanced, thereby preventing the problems of parasitic capacitance and short-circuiting.
The etching selectivity between polysilicon and nitride is higher than that between silicon nitride and silicon oxide. In this way, the thickness of the spacer can be effectively reduced and the degree of integration increased while providing the same degree of protection to the gate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.